An integrated circuit comprises electrical components such as transistors formed on a substrate, the electrical components connected by conductive paths called interconnects. The integrated circuit is typically covered with a protective overcoat layer to protect the circuit from moisture and mechanical damage. In certain applications, such as for high current, MOSFETs, a thick conductive layer may be used to form a low-resistance path over the protective overcoat through which to conduct high current that cannot be accommodated at lower interconnect levels.
When certain materials are used for the top conductor, for example copper, the top conductor may have significant residual stress at room temperature due to the nature of processing of the layer. Certain metallic thin films typically have a high tensile stress at room temperature because they have been annealed at a higher temperature, at which the zero thermal stress point is set. When the wafer cools, the stress in the top conductor becomes tensile due to the metal's greater coefficient of thermal expansion than the substrate, which is typically silicon. When significant areas of uninterrupted top conductor material remain after patterning the level, the accumulated stress of these areas can induce significant deformation of the wafer, causing it to curve in such a way that subsequent processing tools may not be able to properly handle the wafer. Moreover, the presence of the stress makes the wafer more prone to breakage in later steps, especially when the wafer is thinned prior to sawing for packaging. These problems have the effect of causing wafer loss and increased cycle time, which are economically undesirable in an industry for which the profit margin on commodity products is typically small.
Turning to FIG. 1, illustrated is a top view of a semiconductor device 100 that might experience the tensile stress issues previously discussed. The semiconductor device 100 of FIG. 1 includes bond pads 110 and low-resistance interconnects 120. FIG. 1 illustrates the extent of coverage by the top metallization, e.g., the combination of bond pads 110 and low-resistance interconnects 120. As illustrated, this is a significant fraction of the total area of the product. While FIG. 1 illustrates a device with about 60% coverage, future devices are anticipated to utilize 80% or more coverage by the top metallization. Bond pads 110 typically have an edge length of about 60-90 μm, while the low-resistance interconnects 120 may span almost the entire length of a device die, which may be hundreds to thousands of microns.
While any tensile layer will exert a force on the substrate upon which it is fabricated, the amount of transmitted force increases both with greater degree of coverage and with longer uninterrupted expanses of the layer. Thus, for example, the bond pads 110 will transmit less force to the substrate than will the larger low-resistance interconnects 120.
Turning now to FIGS. 2A, illustrated is a top view of a wafer 200 experiencing bowing as a result of the aforementioned tensile stress. The wafer 200 illustrated in FIG. 2A contains a plurality of semiconductor devices 100, such as those illustrated in FIG. 1. As further shown, the wafer 200 is experiencing stress vectors 210, which may represent the net force transmitted to the wafer by the combined effect of the top metallization of the individual die, for example including the bond pads 110 and the low-resistance interconnects 120.
Turning now to FIG. 2B, illustrated is a side view of the wafer 200 illustrated in FIG. 2A. FIG. 2B further illustrates the curvature induced on wafer 200 by stress vectors 210. The curvature illustrated can result in a vertical displacement of the edge of the wafer 200, relative to the center, of 300 μm for a full thickness 200 mm wafer. This displacement is sufficient to cause unreliable wafer handling in some fabrication tools. After the wafer 200 is thinned prior to separating the semiconductor devices 100, edge displacement typically increases, and can exceed 3-5 mm. This obviously increases the severity of manufacturing issues and may threaten the structural integrity of the wafer 200.
Certain stress reduction methods to reduce the effects of the tensile stress are well known. One such method involves removing portions of the low-resistance interconnects 120 to reduce the extent of uninterrupted metal. While such a method will reduce the stress and the resulting wafer bow, the method is undesirable in high-current applications because it reduces the conductive cross-section of the interconnect, increasing resistance and power dissipation.
Consequently, what is needed in the art is a new method for manufacturing metallization schemes that does not experience the aforementioned drawbacks of the prior art.